ch; jeffreyalaw; christoph.muellner
主题： 回复：回复：[PATCH v3 0/6] RISC-V: Support XTheadVector extension
Hi Juzhe,
Sorry but I'm not quite familiar with the group_overlap framework. Could you
take this pattern as an example to show how to disable an alternative in s
日(星期五) 18:32
收件人："cooper.joshua";
"gcc-patches"
抄 送：Jim Wilson; palmer;
andrew; "philipp.tomsich";
jeffreyalaw;
"christoph.muellner";
jinma; "cooper.qu"
主 题：Re: 回复：[PATCH v3 0/6] RISC-V: Support XTheadVector extension
Yeah.
(define_insn "@pre
On 12/22/23 01:07, juzhe.zh...@rivai.ai wrote:
You mean theadvector doesn't want the current RVV1.0 register overlap
magic as follows ?
*
The destination EEW is smaller than the source EEW and the overlap
is in the lowest-numbered part of the source register group (e.g.,
when
ot; "4")
(set (attr "avl_type_idx") (const_int 5))])
You should use an attribute to disable alternative 0 and alternative 1
constraint.
juzhe.zh...@rivai.ai
发件人： joshua
发送时间： 2023-12-22 18:29
收件人： juzhe.zh...@rivai.ai; gcc-patches
抄送： Jim Wilson; palmer; andrew; philipp.tomsich
---------------------
发件人：juzhe.zh...@rivai.ai
发送时间：2023年12月22日(星期五) 16:07
收件人："cooper.joshua";
"gcc-patches"
抄 送：Jim Wilson; palmer;
andrew; "philipp.tomsich";
jeffreyalaw;
"christoph.muellner";
jinma; "cooper.qu"
送："jim.wilson.gcc"; palmer;
andrew; "philipp.tomsich"; Jeff
Law; "Christoph Müllner";
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jinma; Cooper Qu
主 题：Re: [PATCH v3 0/6] RISC-V: Support XTheadVector extension
Hi, Joshua.
Thanks for working hard on clean up codes and support ton
; "philipp.tomsich"; Jeff
Law; "Christoph Müllner";
"cooper.joshua";
jinma; Cooper Qu
主 题：Re: [PATCH v3 0/6] RISC-V: Support XTheadVector extension
Hi, Joshua.
Thanks for working hard on clean up codes and support tons of work on
theadvector.
After fully review this pat
On 12/20/23 20:30, juzhe.zh...@rivai.ai wrote:
OK. Sounds reasonable.
But from my side, I used to commit patches after full coverage testing.
Understood. And it's appreciated -- the code you're doing hits a wide
variety of configurations, so the wider testing is probably applicable.
Idea
: [PATCH v3 0/6] RISC-V: Support XTheadVector extension
On 12/20/23 16:08, 钟居哲 wrote:
> Btw, rv32/rv64gc or rv32/rv64 gcv testing is not enough.
>
> We need full coverage testing, since we always commit patch after no
> regression testing on full coverage testing:
No. It is unr
On 12/20/23 16:08, 钟居哲 wrote:
Btw, rv32/rv64gc or rv32/rv64 gcv testing is not enough.
We need full coverage testing, since we always commit patch after no
regression testing on full coverage testing:
No. It is unreasonable to require this large of test matrix for the
vast majority if cont
; andrew; philipp.tomsich; jeffreyalaw;
christoph.muellner; juzhe.zhong; Jun Sha (Joshua); Jin Ma; Xianmiao Qu
Subject: [PATCH v3 0/6] RISC-V: Support XTheadVector extension
This patch series presents gcc implementation of the XTheadVector
extension [1].
[1] https://github.com/T-head-Semi/thead
uctions from
attribute:
(set_attr "type" "vlds")
juzhe.zh...@rivai.ai
From: Jun Sha (Joshua)
Date: 2023-12-20 20:20
To: gcc-patches
CC: jim.wilson.gcc; palmer; andrew; philipp.tomsich; jeffreyalaw;
christoph.muellner; juzhe.zhong; Jun Sha (Joshua); Jin Ma; Xianmiao Qu
Su
This patch series presents gcc implementation of the XTheadVector
extension [1].
[1] https://github.com/T-head-Semi/thead-extension-spec/
For some vector patterns that cannot be avoided, we use
"!TARGET_XTHEADVECTOR" to disable them in order not to
generate instructions that xtheadvector does not
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