Re: [PATCH v3] RISC-V: use fclass insns to implement isfinite,isnormal and isinf builtins

2024-07-12 Thread Vineet Gupta
On 7/12/24 14:52, Jeff Law wrote: >> +(define_insn "*fclass" >> + [(set (match_operand:X 0 "register_operand" "=r") >> +(unspec [(match_operand:ANYF 1 "register_operand" " f")] >> + UNSPEC_FCLASS))] >> + "TARGET_HARD_FLOAT" >> + "fclass.\t%0,%1"; >> + [(set_attr "type"

Re: [PATCH v3] RISC-V: use fclass insns to implement isfinite,isnormal and isinf builtins

2024-07-12 Thread Jeff Law
On 7/12/24 3:12 PM, Vineet Gupta wrote: Changes since v2: - fclass define_insn tightened to check op0 mode "X" with additional expander w/o mode for callers. - builtins expander explicit mode check and FAIL if mode not appropriate. - subreg promoted handling to elide potential ex

[PATCH v3] RISC-V: use fclass insns to implement isfinite, isnormal and isinf builtins

2024-07-12 Thread Vineet Gupta
Changes since v2: - fclass define_insn tightened to check op0 mode "X" with additional expander w/o mode for callers. - builtins expander explicit mode check and FAIL if mode not appropriate. - subreg promoted handling to elide potential extension of ret val. - Added isinf builtin with