Re: [PATCH v3] RISC-V: Fix wrong LMUL when only implict zve32f.

2025-04-01 Thread Robin Dapp
Note it's not quite "whatever" -- there is a constraint that vl be monotonically nonincreasing, which in some cases is the only important property. No denying this is an annoyance, though. Yes, I was hoping the smiley would convey that "whatever" was not to be taken literally. In terms of SC

Re: [PATCH v3] RISC-V: Fix wrong LMUL when only implict zve32f.

2025-04-01 Thread Andrew Waterman
On Mon, Mar 31, 2025 at 11:34 PM Robin Dapp wrote: > > >> Yeah...and I also don't like the magic "ceil(AVL / 2) ≤ vl ≤ VLMAX if > >> AVL < (2 * VLMAX)" rule... > > > > +1, spec has some description about this but I am not sure if I really get > > the point. > > > > From Spec: > > > > "For exampl

Re: [PATCH v3] RISC-V: Fix wrong LMUL when only implict zve32f.

2025-03-31 Thread Robin Dapp
Yeah...and I also don't like the magic "ceil(AVL / 2) ≤ vl ≤ VLMAX if AVL < (2 * VLMAX)" rule... +1, spec has some description about this but I am not sure if I really get the point. From Spec: "For example, this permits an implementation to set vl = ceil(AVL / 2) for VLMAX <

RE: [PATCH v3] RISC-V: Fix wrong LMUL when only implict zve32f.

2025-03-31 Thread Li, Pan2
Kito Cheng Sent: Tuesday, April 1, 2025 9:53 AM To: Robin Dapp Cc: Kito Cheng ; gcc-patches@gcc.gnu.org; pal...@dabbelt.com; jeffreya...@gmail.com; rd...@ventanamicro.com; juzhe.zh...@rivai.ai; Li, Pan2 ; vine...@rivosinc.com; patr...@rivosinc.com; monk.chi...@sifive.com Subject: Re: [PATCH v3

Re: [PATCH v3] RISC-V: Fix wrong LMUL when only implict zve32f.

2025-03-31 Thread Kito Cheng
Hi Robin: Pushed to trunk, thanks, On Mon, Mar 31, 2025 at 11:23 PM Robin Dapp wrote: > > LGTM (even though I still don't like the spec :D). Yeah...and I also don't like the magic "ceil(AVL / 2) ≤ vl ≤ VLMAX if AVL < (2 * VLMAX)" rule... > We still have an implicit assumption in riscv-vsetvl.

[PATCH v3] RISC-V: Fix wrong LMUL when only implict zve32f.

2025-03-31 Thread Kito Cheng
From: Monk Chiang According to Section 3.4.2, Vector Register Grouping, in the RISC-V Vector Specification, the rule for LMUL is LMUL >= SEW/ELEN Changes since V2: - Add check on vector-iterators.md - Add one more testcase to check the VLS use correct mode. gcc/ChangeLog: * config/riscv

Re: [PATCH v3] RISC-V: Fix wrong LMUL when only implict zve32f.

2025-03-31 Thread Robin Dapp
LGTM (even though I still don't like the spec :D). We still have an implicit assumption in riscv-vsetvl.cc that might modify LMUL: In prev_ratio_valid_for_next_sew_p and next_ratio_valid_for_prev_sew_p we check whether the ratio of two LMULs is <= 8. ISTR that with recent changes we only re-u