Pushed r13-4259.
在 2022/11/16 10:10, Lulu Cheng 写道:
v2 -> v3:
1. Remove preldx support.
---
Enable sw prefetching at -O3 and higher.
Co-Authored-By: xujiahao
gcc/ChangeLog:
* config/loongarch/constraints.md (ZD): New constraint.
* config/l
LGTM. A minor issue is "enabling -fprefetch-loop-arrays at -O3" is not
documented, but AArch64 and i386 are already doing this anyway. We can
add the fact into the doc later.
On Wed, 2022-11-16 at 10:10 +0800, Lulu Cheng wrote:
> v2 -> v3:
> 1. Remove preldx support.
>
> ---
On Wed, 2022-11-16 at 11:19 +0800, Lulu Cheng wrote:
> The "m" constraint is defined as follows:
> (define_memory_constraint "m"
> (and (match_code "mem")
> (match_test "loongarch_12bit_offset_address_p (XEXP (op, 0),
> mode)")))
> This setting must be a memory operand.
> ''ZD" constrain
在 2022/11/16 上午11:06, WANG Xuerui 写道:
On 2022/11/16 10:10, Lulu Cheng wrote:
v2 -> v3:
1. Remove preldx support.
---
Enable sw prefetching at -O3 and higher.
Co-Authored-By: xujiahao
gcc/ChangeLog:
* config/loongarch/constraints.md (ZD): New constr
On 2022/11/16 10:10, Lulu Cheng wrote:
v2 -> v3:
1. Remove preldx support.
---
Enable sw prefetching at -O3 and higher.
Co-Authored-By: xujiahao
gcc/ChangeLog:
* config/loongarch/constraints.md (ZD): New constraint.
* config/loongarch/loo
v2 -> v3:
1. Remove preldx support.
---
Enable sw prefetching at -O3 and higher.
Co-Authored-By: xujiahao
gcc/ChangeLog:
* config/loongarch/constraints.md (ZD): New constraint.
* config/loongarch/loongarch-def.c: Initial number of parallel pr
