Re: [PATCH v2 2/4] RISC-V: Cover sign-extensions in lshrsi3_zero_extend_2

2024-05-08 Thread Jeff Law
On 5/8/24 1:36 AM, Christoph Müllner wrote: The pattern lshrsi3_zero_extend_2 extracts the MSB bits of the lower 32-bit word and zero-extends it back to DImode. This is realized using srliw, which operates on 32-bit registers. The same optimziation can be applied to sign-extensions when emitt

[PATCH v2 2/4] RISC-V: Cover sign-extensions in lshrsi3_zero_extend_2

2024-05-08 Thread Christoph Müllner
The pattern lshrsi3_zero_extend_2 extracts the MSB bits of the lower 32-bit word and zero-extends it back to DImode. This is realized using srliw, which operates on 32-bit registers. The same optimziation can be applied to sign-extensions when emitting a sraiw instead of the srliw. Given these tw