Re: [PATCH v2 1/2] RISC-V: Add basic support for the Ventana-VT1 core

Applied to master. Thanks! Philipp. On Mon, 14 Nov 2022 at 16:52, Jeff Law wrote: > > > On 11/13/22 13:48, Philipp Tomsich wrote: > > The Ventana-VT1 core is compatible with rv64gc, Zb[abcs], Zifenci and > > XVentanaCondOps. > > This introduces a placeholder -mcpu=ventana-vt1, so tooling and > >

Re: [PATCH v2 1/2] RISC-V: Add basic support for the Ventana-VT1 core

On Mon, 14 Nov 2022 at 16:52, Jeff Law wrote: > > > On 11/13/22 13:48, Philipp Tomsich wrote: > > The Ventana-VT1 core is compatible with rv64gc, Zb[abcs], Zifenci and > > XVentanaCondOps. > > This introduces a placeholder -mcpu=ventana-vt1, so tooling and > > scripts don't need to change once ful

Re: [PATCH v2 1/2] RISC-V: Add basic support for the Ventana-VT1 core

On 11/13/22 13:48, Philipp Tomsich wrote: The Ventana-VT1 core is compatible with rv64gc, Zb[abcs], Zifenci and XVentanaCondOps. This introduces a placeholder -mcpu=ventana-vt1, so tooling and scripts don't need to change once full support (pipeline, tuning, etc.) will become public later. gcc

[PATCH v2 1/2] RISC-V: Add basic support for the Ventana-VT1 core

The Ventana-VT1 core is compatible with rv64gc, Zb[abcs], Zifenci and XVentanaCondOps. This introduces a placeholder -mcpu=ventana-vt1, so tooling and scripts don't need to change once full support (pipeline, tuning, etc.) will become public later. gcc/ChangeLog: * config/riscv/riscv-core