Applied to master (with the change from the reviews), thanks!
Philipp.
On Mon, 19 Dec 2022 at 07:30, Kito Cheng wrote:
> just one more nit: Use INVALID_REGNUM as sentinel value for
> riscv_next_saved_reg, otherwise LGTM, and feel free to commit that
> separately :)
>
> On Mon, Dec 19, 2022 at 9
On Mon, Dec 19, 2022 at 7:30 AM Kito Cheng wrote:
> just one more nit: Use INVALID_REGNUM as sentinel value for
> riscv_next_saved_reg, otherwise LGTM, and feel free to commit that
> separately :)
>
Would this change below be ok?
@@ -5540,7 +5540,7 @@ riscv_next_saved_reg (unsigned int regno, u
On Mon, Dec 19, 2022 at 10:26 AM Kito Cheng wrote:
> Something like this:
>
> static unsigned int
> riscv_next_saved_reg (unsigned int regno, unsigned int limit,
> HOST_WIDE_INT *offset, bool inc = true)
> {
> if (inc)
> regno++;
>
> while (regno <= limit)
> {
>
Something like this:
static unsigned int
riscv_next_saved_reg (unsigned int regno, unsigned int limit,
HOST_WIDE_INT *offset, bool inc = true)
{
if (inc)
regno++;
while (regno <= limit)
{
if (BITSET_P (cfun->machine->frame.mask, regno - GP_REG_FIRST))
just one more nit: Use INVALID_REGNUM as sentinel value for
riscv_next_saved_reg, otherwise LGTM, and feel free to commit that
separately :)
On Mon, Dec 19, 2022 at 9:08 AM Christoph Muellner
wrote:
>
> From: Christoph Müllner
>
> This patch restructures the loop over the GP registers
> which sa
From: Christoph Müllner
This patch restructures the loop over the GP registers
which saves/restores then as part of the prologue/epilogue.
No functional change is intended by this patch, but it
offers the possibility to use load-pair/store-pair instructions.
gcc/ChangeLog:
* config/risc
