On 10/20/22 13:01, Andrea Parri wrote:
On Wed, Oct 12, 2022 at 07:16:20PM +0200, Andrea Parri wrote:
+Andrea, in case he has time to look at the memory model / ABI
issues.
+Jeff, who was offering to help when the threads got crossed. I'd punted on
a lot of this in the hope Andrea c
On Wed, Oct 12, 2022 at 07:16:20PM +0200, Andrea Parri wrote:
> > > > +Andrea, in case he has time to look at the memory model / ABI
> > > > issues.
>
> > +Jeff, who was offering to help when the threads got crossed. I'd punted on
> > a lot of this in the hope Andrea could help out, as I'
On Fri, 14 Oct 2022 14:57:22 PDT (-0700), Palmer Dabbelt wrote:
On Fri, 14 Oct 2022 13:39:33 PDT (-0700), jeffreya...@gmail.com wrote:
On 10/14/22 05:03, Christoph Müllner wrote:
My guess is people like the ISA mapping (more) because it has been
documented and reviewed.
And it is the product
On Fri, 14 Oct 2022 13:39:33 PDT (-0700), jeffreya...@gmail.com wrote:
On 10/14/22 05:03, Christoph Müllner wrote:
My guess is people like the ISA mapping (more) because it has been
documented and reviewed.
And it is the product of a working group that worked out the
RVWMO specification.
Thi
On 10/14/22 05:03, Christoph Müllner wrote:
My guess is people like the ISA mapping (more) because it has been
documented and reviewed.
And it is the product of a working group that worked out the
RVWMO specification.
This gives some confidence that we don't need to rework it massively
beca
On Fri, Oct 14, 2022 at 1:15 AM Palmer Dabbelt wrote:
> On Thu, 13 Oct 2022 15:39:39 PDT (-0700), gcc-patches@gcc.gnu.org wrote:
> >
> > On 10/11/22 17:31, Vineet Gupta wrote:
> >>
> >>>
> >>> I expect that the pressure for a proper fix upstream (instead of a
> >>> backward compatible compromise)
On 10/13/22 15:39, Jeff Law via Gcc-patches wrote:
On 10/11/22 17:31, Vineet Gupta wrote:
I expect that the pressure for a proper fix upstream (instead of a
backward compatible compromise) will increase over time (once people
start building big iron based on RISC-V and start hunting perfor
On Thu, 13 Oct 2022 15:39:39 PDT (-0700), gcc-patches@gcc.gnu.org wrote:
On 10/11/22 17:31, Vineet Gupta wrote:
I expect that the pressure for a proper fix upstream (instead of a
backward compatible compromise) will increase over time (once people
start building big iron based on RISC-V and
On 10/12/22 02:03, Christoph Müllner wrote:
So we have the following atomics ABIs:
I) GCC implementation
II) LLVM implementation
III) Specified ABI in the "Code Porting and Mapping Guidelines"
appendix of the RISC-V specification
And presumably we don't have any way to distinguish betwe
On 10/11/22 18:15, Palmer Dabbelt wrote:
Sorry, I thought we'd talked about it somewhere but it must have just
been in meetings and such. Patrick was writing a similar patch set
around the same time so it probably just got tied up in that, we ended
up reducing it to just the strong CAS inl
On 10/11/22 17:31, Vineet Gupta wrote:
I expect that the pressure for a proper fix upstream (instead of a
backward compatible compromise) will increase over time (once people
start building big iron based on RISC-V and start hunting performance
bottlenecks in multithreaded workloads to be
> > > +Andrea, in case he has time to look at the memory model / ABI
> > > issues.
> +Jeff, who was offering to help when the threads got crossed. I'd punted on
> a lot of this in the hope Andrea could help out, as I'm not really a memory
> model guy and this is pretty far down the rabbit
On Wed, Oct 12, 2022 at 2:15 AM Palmer Dabbelt wrote:
> On Tue, 11 Oct 2022 16:31:25 PDT (-0700), Vineet Gupta wrote:
> >
> >
> > On 10/11/22 13:46, Christoph Müllner wrote:
> >> On Tue, Oct 11, 2022 at 9:31 PM Palmer Dabbelt
> wrote:
> >>
> >> On Tue, 11 Oct 2022 12:06:27 PDT (-0700), Vinee
On Tue, 11 Oct 2022 16:31:25 PDT (-0700), Vineet Gupta wrote:
On 10/11/22 13:46, Christoph Müllner wrote:
On Tue, Oct 11, 2022 at 9:31 PM Palmer Dabbelt wrote:
On Tue, 11 Oct 2022 12:06:27 PDT (-0700), Vineet Gupta wrote:
> Hi Christoph, Kito,
>
> On 5/5/21 12:36, Christoph M
On 10/11/22 13:46, Christoph Müllner wrote:
On Tue, Oct 11, 2022 at 9:31 PM Palmer Dabbelt wrote:
On Tue, 11 Oct 2022 12:06:27 PDT (-0700), Vineet Gupta wrote:
> Hi Christoph, Kito,
>
> On 5/5/21 12:36, Christoph Muellner via Gcc-patches wrote:
>> This series provides a c
On 10/11/22 13:31, Palmer Dabbelt wrote:
On Tue, 11 Oct 2022 12:06:27 PDT (-0700), Vineet Gupta wrote:
Hi Christoph, Kito,
On 5/5/21 12:36, Christoph Muellner via Gcc-patches wrote:
This series provides a cleanup of the current atomics implementation
of RISC-V:
* PR100265: Use proper fences
On Tue, Oct 11, 2022 at 9:31 PM Palmer Dabbelt wrote:
> On Tue, 11 Oct 2022 12:06:27 PDT (-0700), Vineet Gupta wrote:
> > Hi Christoph, Kito,
> >
> > On 5/5/21 12:36, Christoph Muellner via Gcc-patches wrote:
> >> This series provides a cleanup of the current atomics implementation
> >> of RISC-V
On Tue, 11 Oct 2022 12:06:27 PDT (-0700), Vineet Gupta wrote:
Hi Christoph, Kito,
On 5/5/21 12:36, Christoph Muellner via Gcc-patches wrote:
This series provides a cleanup of the current atomics implementation
of RISC-V:
* PR100265: Use proper fences for atomic load/store
* PR100266: Provide p
Hi Christoph, Kito,
On 5/5/21 12:36, Christoph Muellner via Gcc-patches wrote:
This series provides a cleanup of the current atomics implementation
of RISC-V:
* PR100265: Use proper fences for atomic load/store
* PR100266: Provide programmatic implementation of CAS
As both are very related, I
This series provides a cleanup of the current atomics implementation
of RISC-V:
* PR100265: Use proper fences for atomic load/store
* PR100266: Provide programmatic implementation of CAS
As both are very related, I merged the patches into one series.
The first patch could be squashed into the fo
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