Re: [PATCH v2] x86: Add a pass to remove redundant all 0s/1s vector load

2025-04-28 Thread H.J. Lu
On Tue, Apr 29, 2025 at 10:08 AM Hongtao Liu wrote: > > On Mon, Apr 28, 2025 at 5:07 PM H.J. Lu wrote: > > > > On Mon, Apr 28, 2025 at 4:26 PM H.J. Lu wrote: > > > > > > > > > > This is what my patch does: > > > > But it iterates through vector_insns, using a def-ref chain to find > > > > those

Re: [PATCH v2] x86: Add a pass to remove redundant all 0s/1s vector load

2025-04-28 Thread Hongtao Liu
On Mon, Apr 28, 2025 at 5:07 PM H.J. Lu wrote: > > On Mon, Apr 28, 2025 at 4:26 PM H.J. Lu wrote: > > > > > > > This is what my patch does: > > > But it iterates through vector_insns, using a def-ref chain to find > > > those insns. I think we can just record those single_set with src as > > > co

[PATCH v2] x86: Add a pass to remove redundant all 0s/1s vector load

2025-04-28 Thread H.J. Lu
an SSE register, then tie with > any other mode acceptable to SSE registers, excluding > (subreg:QI (reg:TI 99) 0)) > (subreg:HI (reg:TI 99) 0)) > (subreg:SI (reg:TI 99) 0)) > (subreg:DI (reg:TI 99) 0)) > to avoid unnecessary move from SSE