On 7/31/23 06:14, Wang, Yanzhang wrote:
Thanks your comments, Jeff and Robin
Is the mulh case somehow common or critical?
Well, I would actually back up even further. What were the
circumstances that led to the mulh with a zero operand?
I think you both mentioned why should we add the mu
Jeff Law
> Sent: Saturday, July 29, 2023 7:07 AM
> To: Robin Dapp ; Wang, Yanzhang
> ; gcc-patches@gcc.gnu.org
> Cc: juzhe.zh...@rivai.ai; kito.ch...@sifive.com; Li, Pan2
>
> Subject: Re: [PATCH v2] RISC-V: convert the mulh with 0 to mov 0 to the reg.
>
>
>
> On
On 7/28/23 06:31, Robin Dapp via Gcc-patches wrote:
This is a draft patch. I would like to explain it's hard to make the
simplify generic and ask for some help.
There're 2 categories we need to optimize.
- The op in optab such as div / 1.
- The unspec operation such as mulh * 0, (vadc+vmadc)
> This is a draft patch. I would like to explain it's hard to make the
> simplify generic and ask for some help.
>
> There're 2 categories we need to optimize.
>
> - The op in optab such as div / 1.
> - The unspec operation such as mulh * 0, (vadc+vmadc) + 0.
>
> Especially for the unspec operat
essage-
> From: Wang, Yanzhang
> Sent: Friday, July 28, 2023 7:50 PM
> To: gcc-patches@gcc.gnu.org
> Cc: juzhe.zh...@rivai.ai; kito.ch...@sifive.com; rdapp@gmail.com; Li,
> Pan2 ; Wang, Yanzhang
> Subject: [PATCH v2] RISC-V: convert the mulh with 0 to mov 0 to the reg.
>
於 2023年7月28日 週五 19:50 寫道：
> From: Yanzhang Wang
>
> This patch will optimize the below mulh example,
>
> vint32m1_t shortcut_for_riscv_vmulh_case_0(vint32m1_t v1, size_t vl) {
> return __riscv_vmulh_vx_i32m1(v1, 0, vl);
> }
>
> from mulh pattern
>
> vsetvli zero, a2, e32, m1, ta, ma
> vmulh.
From: Yanzhang Wang
This patch will optimize the below mulh example,
vint32m1_t shortcut_for_riscv_vmulh_case_0(vint32m1_t v1, size_t vl) {
return __riscv_vmulh_vx_i32m1(v1, 0, vl);
}
from mulh pattern
vsetvli zero, a2, e32, m1, ta, ma
vmulh.vx v24, v24, zero
vs1r.vv24, 0(a0)
to belo
