Re: Re: [PATCH v2] RISC-V: Support scheduling for sifive p600 series

patches; kito.cheng > Subject: Re: [PATCH v2] RISC-V: Support scheduling for sifive p600 series > Hi Juzhe, > The vector part is complicated, I will add it last. > > On Thu, Feb 1, 2024 at 11:08 AM juzhe.zh...@rivai.ai > wrote: >> >> Hi, Monk. >> >> T

Re: [PATCH v2] RISC-V: Support scheduling for sifive p600 series

thanks, pushed to trunk :) On Thu, Feb 1, 2024 at 11:02 AM Monk Chiang wrote: > > Add sifive p600 series scheduler module. For more information > see https://www.sifive.com/cores/performance-p650-670. > Add sifive-p650, sifive-p670 for mcpu option will come in separate patches. > > gcc/ChangeLog:

Re: Re: [PATCH v2] RISC-V: Support scheduling for sifive p600 series

Thanks. I wonder whether p600 will enable dynamic lmul by default ? Does dynamic LMUL help with sifive p600 chip ? juzhe.zh...@rivai.ai From: Monk Chiang Date: 2024-02-01 16:10 To: juzhe.zh...@rivai.ai CC: gcc-patches; kito.cheng Subject: Re: [PATCH v2] RISC-V: Support scheduling for sifive

Re: [PATCH v2] RISC-V: Support scheduling for sifive p600 series

Hi Juzhe, The vector part is complicated, I will add it last. On Thu, Feb 1, 2024 at 11:08 AM juzhe.zh...@rivai.ai wrote: > Hi, Monk. > > This model doesn't include vector. Will you add vector pipeline in the > followup patches ? > > -- > juzhe.zh...@rivai.ai >

[PATCH v2] RISC-V: Support scheduling for sifive p600 series

Hi, Monk. This model doesn't include vector. Will you add vector pipeline in the followup patches ? juzhe.zh...@rivai.ai

[PATCH v2] RISC-V: Support scheduling for sifive p600 series

Add sifive p600 series scheduler module. For more information see https://www.sifive.com/cores/performance-p650-670. Add sifive-p650, sifive-p670 for mcpu option will come in separate patches. gcc/ChangeLog: * config/riscv/riscv.md: Add "fcvt_i2f", "fcvt_f2i" type attribute, and in