Committed, thanks Kito and Juzhe.
Pan
-Original Message-
From: Kito Cheng
Sent: Monday, June 5, 2023 4:47 PM
To: juzhe.zh...@rivai.ai
Cc: Li, Pan2 ; gcc-patches ; Wang,
Yanzhang
Subject: Re: [PATCH v2] RISC-V: Support RVV FP16 ZVFH floating-point intrinsic
API
LGTM too, thanks
wang
> Subject: [PATCH v2] RISC-V: Support RVV FP16 ZVFH floating-point intrinsic API
> From: Pan Li
>
> This patch support the intrinsic API of FP16 ZVFH floating-point. Aka
> SEW=16 for below instructions:
>
> vfadd vfsub vfrsub vfwadd vfwsub
> vfmul vfdiv vfrdiv vfwmu
LGTM,
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2023-06-05 16:20
To: gcc-patches
CC: juzhe.zhong; kito.cheng; pan2.li; yanzhang.wang
Subject: [PATCH v2] RISC-V: Support RVV FP16 ZVFH floating-point intrinsic API
From: Pan Li
This patch support the intrinsic API of FP16 ZVFH floating-point
From: Pan Li
This patch support the intrinsic API of FP16 ZVFH floating-point. Aka
SEW=16 for below instructions:
vfadd vfsub vfrsub vfwadd vfwsub
vfmul vfdiv vfrdiv vfwmul
vfmacc vfnmacc vfmsac vfnmsac vfmadd
vfnmadd vfmsub vfnmsub vfwmacc vfwnmacc vfwmsac vfwnmsac
vfsqrt vfrsqrt7 vfrec7
vfmin
