RE: [PATCH v2] RISC-V: Refine the condition for add additional vars in RVV cost model

2024-04-29 Thread Demin Han
gcc.gnu.org> CC: juzhe.zhong<mailto:juzhe.zh...@rivai.ai>; kito.cheng<mailto:kito.ch...@gmail.com>; pan2.li<mailto:pan2...@intel.com>; jeffreyalaw<mailto:jeffreya...@gmail.com>; rdapp.gcc<mailto:rdapp@gmail.com> Subject: [PATCH v2] RISC-V: Refine the conditio

Re: [PATCH v2] RISC-V: Refine the condition for add additional vars in RVV cost model

2024-04-28 Thread juzhe.zh...@rivai.ai
Hi, Han. GCC 14 is branch out. You can commit it to trunk (GCC 15). juzhe.zh...@rivai.ai From: demin.han Date: 2024-04-02 16:30 To: gcc-patches CC: juzhe.zhong; kito.cheng; pan2.li; jeffreyalaw; rdapp.gcc Subject: [PATCH v2] RISC-V: Refine the condition for add additional vars in RVV cost

Re: [PATCH v2] RISC-V: Refine the condition for add additional vars in RVV cost model

2024-04-02 Thread juzhe.zh...@rivai.ai
Thanks for fixing it. LGTM to GCC-15 as Jeff suggested. juzhe.zh...@rivai.ai From: demin.han Date: 2024-04-02 16:30 To: gcc-patches CC: juzhe.zhong; kito.cheng; pan2.li; jeffreyalaw; rdapp.gcc Subject: [PATCH v2] RISC-V: Refine the condition for add additional vars in RVV cost model The

[PATCH v2] RISC-V: Refine the condition for add additional vars in RVV cost model

2024-04-02 Thread demin.han
The adjacent_dr_p is sufficient and unnecessary condition for contiguous access. So unnecessary live-ranges are added and result in smaller LMUL. This patch uses MEMORY_ACCESS_TYPE as condition and constrains segment load/store. Tested on RV64 and no regression. PR target/114506 gcc/Cha