RE: [PATCH v2] RISC-V: Introduce gcc option mrvv-vector-bits for RVV

@gcc.gnu.org; juzhe.zh...@rivai.ai; Wang, Yanzhang ; rdapp@gmail.com; jeffreya...@gmail.com Subject: RE: [PATCH v2] RISC-V: Introduce gcc option mrvv-vector-bits for RVV Oh, I see, that indicates simply convert this option value to riscv_vector_chunks is not good enough here. I thought the term

RE: [PATCH v2] RISC-V: Introduce gcc option mrvv-vector-bits for RVV

...@rivai.ai; Wang, Yanzhang ; rdapp@gmail.com; jeffreya...@gmail.com Subject: Re: [PATCH v2] RISC-V: Introduce gcc option mrvv-vector-bits for RVV Keep SCALABLE, since it has different semantics with ZVL: -mrvv-vector-bits=scalble means zvl*b specify the minimal VLEN -mrvv-vector-bits=zvl means zvl*b

Re: [PATCH v2] RISC-V: Introduce gcc option mrvv-vector-bits for RVV

Keep SCALABLE, since it has different semantics with ZVL: -mrvv-vector-bits=scalble means zvl*b specify the minimal VLEN -mrvv-vector-bits=zvl means zvl*b specify the exactly VLEN What's difference exactly? -mrvv-vector-bits=scalble with zvl128b can run on any machine with VLEN >= 128 -mrvv-vect

[PATCH v2] RISC-V: Introduce gcc option mrvv-vector-bits for RVV

From: Pan Li This patch would like to introduce one new gcc option for RVV. To appoint the bits size of one RVV vector register. Valid arguments to '-mrvv-vector-bits=' are: * zvl The zvl will pick up the zvl*b from the march option. For example, the mrvv-vector-bits will be 1024 when march=rv6