To: Li, Pan2 ; gcc-patches@gcc.gnu.org
Cc: juzhe.zh...@rivai.ai; kito.ch...@gmail.com; rdapp@gmail.com
Subject: Re: [PATCH v2] RISC-V: Implement the .SAT_TRUNC for scalar
On 7/3/24 8:07 PM, Li, Pan2 wrote:
>> But if you look at what the hardware can actually support, it doesn&#
On 7/3/24 8:07 PM, Li, Pan2 wrote:
But if you look at what the hardware can actually support, it doesn't
have HImode or QImode operations other than load/store and for rv64
there are no SImode logicals.
That's what WORD_REGISTER_OPERATIONS is designed to support. Regardless
of what happens
Sent: Thursday, July 4, 2024 10:07 AM
To: Jeff Law ; gcc-patches@gcc.gnu.org
Cc: juzhe.zh...@rivai.ai; kito.ch...@gmail.com; rdapp@gmail.com
Subject: RE: [PATCH v2] RISC-V: Implement the .SAT_TRUNC for scalar
> But if you look at what the hardware can actually support, it doesn't
e_call_set_lhs (call, lhs);
gsi_replace (gsi, call, /* update_eh_info */ true);
}
}
Pan
-Original Message-
From: Jeff Law
Sent: Thursday, July 4, 2024 9:52 AM
To: Li, Pan2 ; gcc-patches@gcc.gnu.org
Cc: juzhe.zh...@rivai.ai; kito.ch...@gmail.com; rdapp....@gmail.com
Subject: Re
On 7/3/24 6:48 PM, Li, Pan2 wrote:
Thanks Jeff for comments.
I would expect that QI/HI shouldn't be happening in practice due to the
definition of WORD_REGISTER_OPERATIONS.
Sorry I don't get the point here, I suppose there may be 6 kinds of truncation
for scalar.
uint64_t => uint32_t
ui
m: Jeff Law
Sent: Wednesday, July 3, 2024 11:14 PM
To: Li, Pan2 ; gcc-patches@gcc.gnu.org
Cc: juzhe.zh...@rivai.ai; kito.ch...@gmail.com; rdapp....@gmail.com
Subject: Re: [PATCH v2] RISC-V: Implement the .SAT_TRUNC for scalar
On 7/2/24 7:16 PM, Li, Pan2 wrote:
> Thanks Jeff for comments.
>
On 7/2/24 7:16 PM, Li, Pan2 wrote:
Thanks Jeff for comments.
Why are you using Pmode? Pmode is for pointers. This stuff looks like
basic integer ops, so I don't see why Pmode is appropriate.
The incoming operand may be HI/QI/SImode, so we need to prompt the mode.
So there we should take
From: Pan Li
This patch would like to implement the simple .SAT_TRUNC pattern
in the riscv backend. Aka:
Form 1:
#define DEF_SAT_U_TRUC_FMT_1(NT, WT) \
NT __attribute__((noinline)) \
sat_u_truc_##WT##_to_##NT##_fmt_1 (WT x) \
{\
M
To: Li, Pan2 ; gcc-patches@gcc.gnu.org
Cc: juzhe.zh...@rivai.ai; kito.ch...@gmail.com; rdapp@gmail.com
Subject: Re: [PATCH v2] RISC-V: Implement the .SAT_TRUNC for scalar
On 7/2/24 12:33 AM, pan2...@intel.com wrote:
>
> The below tests suites are passed for this patch
> 1. The
On 7/2/24 12:33 AM, pan2...@intel.com wrote:
The below tests suites are passed for this patch
1. The rv64gcv fully regression test.
2. The rv64gcv build with glibc
gcc/ChangeLog:
* config/riscv/iterators.md (TARGET_64BIT): Add new iterator
and related attr(s).
Rather than r
From: Pan Li
Update in v2:
Rebase the upstream.
Log in v1:
This patch would like to implement the simple .SAT_TRUNC pattern
in the riscv backend. Aka:
Form 1:
#define DEF_SAT_U_TRUC_FMT_1(NT, WT) \
NT __attribute__((noinline)) \
sat_u_truc_##WT##_to_##NT##_fmt_1 (WT x) \
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