Re: [PATCH v2] RISC-V: Implement .SAT_TRUNC for vector unsigned int

2024-07-07 Thread juzhe.zh...@rivai.ai
+ if (double_mode == E_VOIDmode && quad_mode == E_VOIDmode) Why we have VOID mode ? I still don't understand the codes. juzhe.zh...@rivai.ai From: pan2.li Date: 2024-07-08 12:48 To: gcc-patches CC: juzhe.zhong; kito.cheng; jeffreyalaw; rdapp.gcc; Pan Li Subject: [PATCH v2] RISC

[PATCH v2] RISC-V: Implement .SAT_TRUNC for vector unsigned int

2024-07-07 Thread pan2 . li
From: Pan Li This patch would like to implement the .SAT_TRUNC for the RISC-V backend. With the help of the RVV Vector Narrowing Fixed-Point Clip Instructions. The below SEW(S) are supported: * e64 => e32 * e64 => e16 * e64 => e8 * e32 => e16 * e32 => e8 * e16 => e8 Take below example to see