> Cc: juzhe.zh...@rivai.ai; kito.ch...@sifive.com; Li, Pan2
> ; Wang, Yanzhang
> Subject: [PATCH v2] RISC-V: ICE for vlmul_ext_v intrinsic API
>
> From: Yanzhang Wang
>
> PR 109617
>
> gcc/ChangeLog:
>
> * config/riscv/vector-iterators.md: Support
Kindly ping for this ICE fix.
Pan
-Original Message-
From: Wang, Yanzhang
Sent: Wednesday, April 26, 2023 9:06 PM
To: gcc-patches@gcc.gnu.org
Cc: juzhe.zh...@rivai.ai; kito.ch...@sifive.com; Li, Pan2 ;
Wang, Yanzhang
Subject: [PATCH v2] RISC-V: ICE for vlmul_ext_v intrinsic API
From
From: Yanzhang Wang
PR 109617
gcc/ChangeLog:
* config/riscv/vector-iterators.md: Support VNx2HI and VNX4DI when
MIN_VLEN >= 128.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/vlmul_ext-1.c: New test.
Signed-off-by: Yanzhang Wang
Co-authored-by: Pan Li
---
g
