Committed, thanks Jeff.
Pan
-Original Message-
From: Jeff Law
Sent: Friday, June 16, 2023 11:56 PM
To: juzhe.zh...@rivai.ai; Li, Pan2 ; gcc-patches
Cc: Robin Dapp ; Wang, Yanzhang ;
kito.cheng
Subject: Re: [PATCH v2] RISC-V: Bugfix for RVV integer reduction in ZVE32/64.
On 6/16
On 6/16/23 02:10, juzhe.zh...@rivai.ai wrote:
LGTM. Thanks for fix this bug.
Let's wait for Jeff's final approve.
OK.
jeff
Thanks Juzhe for reviewing, will take care of the FP and widen part soon.
Pan
From: juzhe.zh...@rivai.ai
Sent: Friday, June 16, 2023 4:11 PM
To: Li, Pan2 ; gcc-patches
Cc: Robin Dapp ; jeffreyalaw ; Li,
Pan2 ; Wang, Yanzhang ; kito.cheng
Subject: Re: [PATCH v2] RISC-V: Bugfix for RVV
LGTM. Thanks for fix this bug.
Let's wait for Jeff's final approve.
Thanks.
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2023-06-16 16:09
To: gcc-patches
CC: juzhe.zhong; rdapp.gcc; jeffreyalaw; pan2.li; yanzhang.wang; kito.cheng
Subject: [PATCH v2] RISC-V: Bugfix for RVV integer re
From: Pan Li
The rvv integer reduction has 3 different patterns for zve128+, zve64
and zve32. They take the same iterator with different attributions.
However, we need the generated function code_for_reduc (code, mode1, mode2).
The implementation of code_for_reduc may look like below.
code_for_r
