Committed, thanks Jeff.
Pan
-Original Message-
From: Jeff Law
Sent: Monday, June 19, 2023 9:51 PM
To: 钟居哲 ; Li, Pan2 ; gcc-patches
Cc: rdapp.gcc ; Wang, Yanzhang ;
kito.cheng
Subject: Re: [PATCH v2] RISC-V: Bugfix for RVV float reduction in ZVE32/64
On 6/18/23 07:14, 钟居哲 wrote
On 6/18/23 07:14, 钟居哲 wrote:
Thanks for fixing it for me.
LGTM now.
OK for the trunk.
jeff
t;
CC: juzhe.zhong<mailto:juzhe.zh...@rivai.ai>;
rdapp.gcc<mailto:rdapp@gmail.com>;
jeffreyalaw<mailto:jeffreya...@gmail.com>; pan2.li<mailto:pan2...@intel.com>;
yanzhang.wang<mailto:yanzhang.w...@intel.com>;
kito.cheng<mailto:kito.ch...@gmail.com>
Subject: [PATCH
Thanks for fixing it for me.
LGTM now.
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2023-06-18 10:57
To: gcc-patches
CC: juzhe.zhong; rdapp.gcc; jeffreyalaw; pan2.li; yanzhang.wang; kito.cheng
Subject: [PATCH v2] RISC-V: Bugfix for RVV float reduction in ZVE32/64
From: Pan Li
The rvv integer
From: Pan Li
The rvv integer reduction has 3 different patterns for zve128+, zve64
and zve32. They take the same iterator with different attributions.
However, we need the generated function code_for_reduc (code, mode1, mode2).
The implementation of code_for_reduc may look like below.
code_for_r
