Cool, Thank you!
Pan
-Original Message-
From: Kito Cheng
Sent: Friday, April 28, 2023 8:37 PM
To: Li, Pan2
Cc: gcc-patches@gcc.gnu.org; juzhe.zh...@rivai.ai; Wang, Yanzhang
Subject: Re: [PATCH v2] RISC-V: Allow RVV VMS{Compare}(V1, V1) simplify to VMCLR
pushed, thanks!
pushed, thanks!
; Wang, Yanzhang
Subject: Re: [PATCH v2] RISC-V: Allow RVV VMS{Compare}(V1, V1) simplify to VMCLR
LGTM
I thought it can optimization __riscv_vmseq_vv_i8m8_b1(v1, v1, vl) too, but
don't know why it's not evaluated
(eq:VNx128BI (reg/v:VNx128QI 137 [ v1 ])
(reg/v:VNx128Q
, Yanzhang
Subject: Re: [PATCH v2] RISC-V: Allow RVV VMS{Compare}(V1, V1) simplify to VMCLR
LGTM
I thought it can optimization __riscv_vmseq_vv_i8m8_b1(v1, v1, vl) too, but
don't know why it's not evaluated
(eq:VNx128BI (reg/v:VNx128QI 137 [ v1 ])
(reg/v:VNx128Q
LGTM
I thought it can optimization __riscv_vmseq_vv_i8m8_b1(v1, v1, vl)
too, but don't know why it's not evaluated
(eq:VNx128BI (reg/v:VNx128QI 137 [ v1 ])
(reg/v:VNx128QI 137 [ v1 ]))
to true, anyway, I guess it should be your next step to investigate :)
On Fri, Apr 28, 2023
From: Pan Li
When some RVV integer compare operators act on the same vector
registers without mask. They can be simplified to VMCLR.
This PATCH allow the ne, lt, ltu, gt, gtu to perform such kind
of the simplification by adding one new define_split.
Given we have:
vbool1_t test_shortcut_for_ris
