在 2022/11/1 下午4:02, Xi Ruoyao 写道:
On Tue, 2022-11-01 at 14:19 +0800, Lulu Cheng wrote:
+;; Load immediate to the 32-63 bits of the source register.
+(define_insn_and_split "load_hi32"
+ [(set (match_operand:DI 0 "register_operand" "=r")
+ (ior:DI
+ (and:DI (match_operand:DI 1 "r
On Tue, 2022-11-01 at 14:19 +0800, Lulu Cheng wrote:
> +;; Load immediate to the 32-63 bits of the source register.
> +(define_insn_and_split "load_hi32"
> + [(set (match_operand:DI 0 "register_operand" "=r")
> + (ior:DI
> + (and:DI (match_operand:DI 1 "register_operand" "0")
> +
v1 -> v2:
1. Change the code format.
2. Fix bugs in the code.
Both regression tests and spec2006 passed.
The problem mentioned in the link does not move the four immediate load
instructions out of the loop. It has been optimized. Now, as in the test case,
four immediate load instructions are gene
