LGTM
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2024-06-14 10:13
To: gcc-patches
CC: juzhe.zhong; kito.cheng; jeffreyalaw; rdapp.gcc; Pan Li
Subject: [PATCH v1 8/8] RISC-V: Add testcases for scalar unsigned SAT_SUB form
10
From: Pan Li
After the middle-end support the form 10 of unsigned
From: Pan Li
After the middle-end support the form 10 of unsigned SAT_SUB and
the RISC-V backend implement the scalar .SAT_SUB, add more test
case to cover the form 10 of unsigned .SAT_SUB.
Form 10:
#define SAT_SUB_U_10(T) \
T sat_sub_u_10_##T (T x, T y) \
{ \
T ret; \
T overflow =
