Re: [PATCH v1 5/7] RISC-V: Add testcases for unsigned .SAT_ADD vector form 6

lgtm --Reply to Message-- On Mon, Jun 17, 2024 22:34 PM pan2.li

[PATCH v1 5/7] RISC-V: Add testcases for unsigned .SAT_ADD vector form 6

From: Pan Li After the middle-end support the form 6 of unsigned SAT_ADD and the RISC-V backend implement the .SAT_ADD for vector mode, add more test case to cover the form 6. Form 6: #define DEF_VEC_SAT_U_ADD_FMT_6(T) \ void __attribute__((noinline))