Re: [PATCH v1 4/8] RISC-V: Add testcases for unsigned .SAT_SUB vector form 6

lgtm --Reply to Message-- On Wed, Jun 19, 2024 21:17 PM pan2.li

[PATCH v1 4/8] RISC-V: Add testcases for unsigned .SAT_SUB vector form 6

From: Pan Li After the middle-end support the form 6 of unsigned SAT_SUB and the RISC-V backend implement the .SAT_SUB for vector mode, thus add more test case to cover that. Form 6: #define DEF_VEC_SAT_U_SUB_FMT_6(T) \ void __attribute__((noinline))