LGTM. Thanks.
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2024-06-03 11:09
To: gcc-patches
CC: juzhe.zhong; kito.cheng; Pan Li
Subject: [PATCH v1 3/5] RISC-V: Add testcases for scalar unsigned SAT_ADD form 3
From: Pan Li
After the middle-end support the form 3 of unsigned SAT_ADD and
the RISC
From: Pan Li
After the middle-end support the form 3 of unsigned SAT_ADD and
the RISC-V backend implement the scalar .SAT_ADD, add more test
case to cover the form 3 of unsigned .SAT_ADD.
Form 3:
#define SAT_ADD_U_3(T) \
T sat_add_u_3_##T (T x, T y) \
{ \
T ret; \
return __builtin_
