LGTM
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2024-10-11 14:22
To: gcc-patches
CC: richard.guenther; Tamar.Christina; juzhe.zhong; kito.cheng; jeffreyalaw;
rdapp.gcc; Pan Li
Subject: [PATCH v1 3/4] RISC-V: Implement vector SAT_SUB for signed integer
From: Pan Li
This patch would like to
From: Pan Li
This patch would like to implement the sssub for vector signed integer.
Form 1:
#define DEF_VEC_SAT_S_SUB_FMT_1(T, UT, MIN, MAX) \
void __attribute__((noinline)) \
vec_sat_s_add_##T##_fmt_1 (T *out, T *op_1, T *op_2, un
