Committed the series, thanks Juzhe.
Pan
From: 钟居哲
Sent: Wednesday, June 19, 2024 12:01 PM
To: Li, Pan2 ; gcc-patches
Cc: kito.cheng ; jeffreyalaw ;
rdapp.gcc ; Li, Pan2
Subject: Re: [PATCH v1 2/7] RISC-V: Add testcases for unsigned .SAT_ADD vector
form 3
lgtm
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lgtm
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On Mon, Jun 17, 2024 22:34 PM pan2.li
From: Pan Li
After the middle-end support the form 3 of unsigned SAT_ADD and
the RISC-V backend implement the .SAT_ADD for vector mode, add
more test case to cover the form 3.
Form 3:
#define DEF_VEC_SAT_U_ADD_FMT_3(T) \
void __attribute__((noinline))
