Re: [PATCH v1 2/3] RISC-V: Split slli+sh[123]add.uw opportunities to avoid zext.w

2022-06-17 Thread Philipp Tomsich
Kito, thanks: you were a few minutes ahead of my fix there. On Fri, 17 Jun 2022 at 16:00, Kito Cheng wrote: > Hi Andreas: > > Fixed via > https://gcc.gnu.org/git/?p=gcc.git;a=commit;h=d6b423882a05d7b4f40ae1e9d942c9c4c13761b7 > , > thanks! > > On Fri, Jun 17, 2022 at 4:34 PM Andreas Schwab > wro

Re: [PATCH v1 2/3] RISC-V: Split slli+sh[123]add.uw opportunities to avoid zext.w

2022-06-17 Thread Kito Cheng via Gcc-patches
Hi Andreas: Fixed via https://gcc.gnu.org/git/?p=gcc.git;a=commit;h=d6b423882a05d7b4f40ae1e9d942c9c4c13761b7, thanks! On Fri, Jun 17, 2022 at 4:34 PM Andreas Schwab wrote: > > ../../gcc/config/riscv/bitmanip.md: In function 'rtx_insn* > gen_split_44(rtx_ins\ > n*, rtx_def**)': > ../../gcc/conf

Re: [PATCH v1 2/3] RISC-V: Split slli+sh[123]add.uw opportunities to avoid zext.w

2022-06-17 Thread Andreas Schwab
../../gcc/config/riscv/bitmanip.md: In function 'rtx_insn* gen_split_44(rtx_ins\ n*, rtx_def**)': ../../gcc/config/riscv/bitmanip.md:110:28: error: comparison of integer express\ ions of different signedness: 'int' and 'long unsigned int' [-Werror=sign-compa\ re] 110 | if ((scale + bias)

Re: [PATCH v1 2/3] RISC-V: Split slli+sh[123]add.uw opportunities to avoid zext.w

2022-06-14 Thread Philipp Tomsich
Thanks, applied to master! For [3/3], I'll submit a new standalone patch with the requested changes. On Tue, 7 Jun 2022 at 12:25, Kito Cheng wrote: > > LGTM, you can commit that without [3/3] if you like :) > > On Wed, May 25, 2022 at 5:47 AM Philipp Tomsich > wrote: > > > > When encountering a

Re: [PATCH v1 2/3] RISC-V: Split slli+sh[123]add.uw opportunities to avoid zext.w

2022-06-07 Thread Kito Cheng via Gcc-patches
LGTM, you can commit that without [3/3] if you like :) On Wed, May 25, 2022 at 5:47 AM Philipp Tomsich wrote: > > When encountering a prescaled (biased) value as a candidate for > sh[123]add.uw, the combine pass will present this as shifted by the > aggregate amount (prescale + shift-amount) with

[PATCH v1 2/3] RISC-V: Split slli+sh[123]add.uw opportunities to avoid zext.w

2022-05-24 Thread Philipp Tomsich
When encountering a prescaled (biased) value as a candidate for sh[123]add.uw, the combine pass will present this as shifted by the aggregate amount (prescale + shift-amount) with an appropriately adjusted mask constant that has fewer than 32 bits set. E.g., here's the failing expression seen in c