Re: [PATCH v1 2/2] RISC-V: Add testcases for unsigned .SAT_SUB scalar form 12

lgtm --Reply to Message-- On Tue, Jun 18, 2024 16:25 PM Li, Pan2

[PATCH v1 2/2] RISC-V: Add testcases for unsigned .SAT_SUB scalar form 12

From: Pan Li After the middle-end support the form 12 of unsigned SAT_SUB and the RISC-V backend implement the SAT_SUB for vector mode, add more test case to cover the form 12. Form 12: #define DEF_SAT_U_SUB_FMT_12(T)\ T __attribute__((noinline))