subject:"\[PATCH v1 2\/2\] RISC\-V\: Add testcases for form 2 of signed vector SAT_ADD"

Re: [PATCH v1 2/2] RISC-V: Add testcases for form 2 of signed vector SAT_ADD

2024-09-24 Thread Robin Dapp

LGTM. -- Regards Robin

[PATCH v1 2/2] RISC-V: Add testcases for form 2 of signed vector SAT_ADD

2024-09-20 Thread pan2 . li

From: Pan Li Form 2: #define DEF_VEC_SAT_S_ADD_FMT_2(T, UT, MIN, MAX) \ void __attribute__((noinline)) \ vec_sat_s_add_##T##_fmt_2 (T *out, T *op_1, T *op_2, unsigned limit) \ {