Committed the series as the middle-end patch committed.
Pan
From: Li, Pan2
Sent: Monday, June 3, 2024 11:24 AM
To: juzhe.zh...@rivai.ai; gcc-patches
Cc: kito.cheng
Subject: RE: [PATCH v1 1/5] RISC-V: Add testcases for scalar unsigned SAT_ADD
form 1
Thanks Juzhe, will commit it after the
ito.cheng<mailto:kito.ch...@gmail.com>; Pan Li<mailto:pan2...@intel.com>
Subject: [PATCH v1 1/5] RISC-V: Add testcases for scalar unsigned SAT_ADD form 1
From: Pan Li mailto:pan2...@intel.com>>
After the middle-end support the form 1 of unsigned SAT_ADD and
the RISC-V backend implement
LGTM. Thanks.
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2024-06-03 11:09
To: gcc-patches
CC: juzhe.zhong; kito.cheng; Pan Li
Subject: [PATCH v1 1/5] RISC-V: Add testcases for scalar unsigned SAT_ADD form 1
From: Pan Li
After the middle-end support the form 1 of unsigned SAT_ADD and
the RISC
From: Pan Li
After the middle-end support the form 1 of unsigned SAT_ADD and
the RISC-V backend implement the scalar .SAT_ADD, add more test
case to cover the form 1 of unsigned .SAT_ADD.
Form 1:
#define SAT_ADD_U_1(T) \
T sat_add_u_1_##T(T x, T y) \
{
