Re: [PATCH v1 1/4] RISC-V: Add testcases for unsigned scalar .SAT_ADD IMM form 1

2024-07-01 Thread juzhe.zh...@rivai.ai
LGTM juzhe.zh...@rivai.ai From: pan2.li Date: 2024-07-01 09:35 To: gcc-patches CC: juzhe.zhong; kito.cheng; jeffreyalaw; rdapp.gcc; Pan Li Subject: [PATCH v1 1/4] RISC-V: Add testcases for unsigned scalar .SAT_ADD IMM form 1 From: Pan Li This patch would like to add test cases for the

[PATCH v1 1/4] RISC-V: Add testcases for unsigned scalar .SAT_ADD IMM form 1

2024-06-30 Thread pan2 . li
From: Pan Li This patch would like to add test cases for the unsigned scalar .SAT_ADD IMM form 1. Aka: Form 1: #define DEF_SAT_U_ADD_IMM_FMT_1(T) \ T __attribute__((noinline)) \ sat_u_add_imm_##T##_fmt_1 (T x) \ {\