kito.ch...@gmail.com; rdapp@gmail.com
Subject: Re: [PATCH v1 1/2] RISC-V: Add testcases for unsigned vector .SAT_ADD
IMM form 1
On 7/8/24 8:15 AM, pan2...@intel.com wrote:
> From: Pan Li
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/riscv/rvv/autovec/binop/ve
On 7/8/24 8:15 AM, pan2...@intel.com wrote:
From: Pan Li
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/binop/vec_sat_arith.h: Add help
test macro.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_data.h: New test.
* gcc.target/riscv/rvv/autovec/binop/ve
From: Pan Li
After the middle-end supported the vector mode of .SAT_ADD, add more
testcases to ensure the correctness of RISC-V backend for form 1. Aka:
Form 1:
#define DEF_VEC_SAT_U_ADD_IMM_FMT_1(T, IMM) \
T __attribute__((noinline))
