Committed the series, thanks Juzhe.
Pan
From: 钟居哲
Sent: Wednesday, June 19, 2024 11:55 AM
To: Li, Pan2 ; gcc-patches
Cc: kito.cheng ; jeffreyalaw ;
rdapp.gcc ; Li, Pan2
Subject: Re: [PATCH v1 1/2] RISC-V: Add testcases for unsigned .SAT_SUB scalar
form 11
lgtm
--Reply to
lgtm
--Reply to Message--
On Tue, Jun 18, 2024 16:25 PM Li, Pan2
From: Pan Li
After the middle-end support the form 11 of unsigned SAT_SUB and
the RISC-V backend implement the SAT_SUB for vector mode, add
more test case to cover the form 11.
Form 11:
#define DEF_SAT_U_SUB_FMT_11(T)\
T __attribute__((noinline))
