On Fri, Aug 30, 2024 at 12:16 PM wrote:
>
> From: Pan Li
>
> This patch would like to support the vector signed ssadd pattern
> for the RISC-V backend. Aka
>
> Form 1:
> #define DEF_VEC_SAT_S_ADD_FMT_1(T, UT, MIN, MAX) \
> void __attribute__((noinline))
: [PATCH v1] Vect: Support form 1 of vector signed integer .SAT_ADD
From: Pan Li
This patch would like to support the vector signed ssadd pattern
for the RISC-V backend. Aka
Form 1:
#define DEF_VEC_SAT_S_ADD_FMT_1(T, UT, MIN, MAX) \
void __attribute__((noinline
From: Pan Li
This patch would like to support the vector signed ssadd pattern
for the RISC-V backend. Aka
Form 1:
#define DEF_VEC_SAT_S_ADD_FMT_1(T, UT, MIN, MAX) \
void __attribute__((noinline)) \
vec_sat_s_add_##T##_fmt_1 (T *out, T *x, T *y, unsign
