Re: [PATCH v1] RISC-V: Support IMM for operand 1 of ussub pattern

2024-08-26 Thread Jeff Law
On 8/26/24 4:26 AM, pan2...@intel.com wrote: From: Pan Li This patch would like to allow IMM for the operand 1 of ussub pattern. Aka .SAT_SUB(x, 22) as the below example. Form 2: #define DEF_SAT_U_SUB_IMM_FMT_2(T, IMM) \ T __attribute__((noinline)) \ sat_u_sub_imm##IMM#

[PATCH v1] RISC-V: Support IMM for operand 1 of ussub pattern

2024-08-26 Thread pan2 . li
From: Pan Li This patch would like to allow IMM for the operand 1 of ussub pattern. Aka .SAT_SUB(x, 22) as the below example. Form 2: #define DEF_SAT_U_SUB_IMM_FMT_2(T, IMM) \ T __attribute__((noinline)) \ sat_u_sub_imm##IMM##_##T##_fmt_2 (T x) \ {