Re: [PATCH v1] RISC-V: Refactor gen zero_extend rtx for SAT_* when expand SImode in RV64

2024-09-01 Thread Jeff Law
On 8/30/24 1:23 AM, pan2...@intel.com wrote: From: Pan Li In previous, we have some specially handling for both the .SAT_ADD and .SAT_SUB for unsigned int. There are similar to take care of SImode in RV64 for zero extend. Thus refactor these two helper function into one for possible code d

[PATCH v1] RISC-V: Refactor gen zero_extend rtx for SAT_* when expand SImode in RV64

2024-08-30 Thread pan2 . li
From: Pan Li In previous, we have some specially handling for both the .SAT_ADD and .SAT_SUB for unsigned int. There are similar to take care of SImode in RV64 for zero extend. Thus refactor these two helper function into one for possible code duplication. The below test suite are passed for t