Re: [PATCH v1] RISC-V: RISC-V: Add testcases for form 4 of signed vector SAT_ADD

LGTM juzhe.zh...@rivai.ai From: pan2.li Date: 2024-09-23 13:43 To: gcc-patches CC: juzhe.zhong; kito.cheng; jeffreyalaw; rdapp.gcc; Pan Li Subject: [PATCH v1] RISC-V: RISC-V: Add testcases for form 4 of signed vector SAT_ADD From: Pan Li Form 4: #define DEF_VEC_SAT_S_ADD_FMT_4(T, UT

[PATCH v1] RISC-V: RISC-V: Add testcases for form 4 of signed vector SAT_ADD

From: Pan Li Form 4: #define DEF_VEC_SAT_S_ADD_FMT_4(T, UT, MIN, MAX) \ void __attribute__((noinline)) \ vec_sat_s_add_##T##_fmt_4 (T *out, T *op_1, T *op_2, unsigned limit) \ {