gt;>; kito.cheng
mailto:kito.ch...@gmail.com>>
Subject: Re: [PATCH v1] RISC-V: Fix one bug for floating-point static frm
LGTM
juzhe.zh...@rivai.ai<mailto:juzhe.zh...@rivai.ai>
From: pan2.li<mailto:pan2...@intel.com>
Date: 2023-07-04 13:
Subject: Re: [PATCH v1] RISC-V: Fix one bug for floating-point static frm
LGTM
juzhe.zh...@rivai.ai<mailto:juzhe.zh...@rivai.ai>
From: pan2.li<mailto:pan2...@intel.com>
Date: 2023-07-04 13:50
To: gcc-patches<mailto:gcc-patches@gcc.gnu.org&g
LGTM
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2023-07-04 13:50
To: gcc-patches
CC: juzhe.zhong; rdapp.gcc; jeffreyalaw; pan2.li; yanzhang.wang; kito.cheng
Subject: [PATCH v1] RISC-V: Fix one bug for floating-point static frm
From: Pan Li
This patch would like to fix one bug to align below
From: Pan Li
This patch would like to fix one bug to align below items of spec.
1. By default, the RVV floating-point will take dyn mode.
2. DYN is invalid in FRM register for RVV floating-point.
When mode switching the function entry and exit, it will take DYN as
the frm mode.
Signed-off-by:
