Re: [PATCH v1] RISC-V: Fix asm check for Vector SAT_* due to middle-end change

On 9/10/24 5:03 PM, pan2...@intel.com wrote: From: Pan Li The middle-end change makes the effect on the layout of the assembly for vector SAT_*. This patch would like to fix it and make it robust. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-1.c: Adj

[PATCH v1] RISC-V: Fix asm check for Vector SAT_* due to middle-end change

From: Pan Li The middle-end change makes the effect on the layout of the assembly for vector SAT_*. This patch would like to fix it and make it robust. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-1.c: Adjust asm check and make it robust.