ect: Re: [PATCH v1] RISC-V: Fix ICE for target attributes has different
xlen size
On 2/14/25 11:33 PM, pan2...@intel.com wrote:
> From: Pan Li
>
> This patch would like to avoid the ICE when the target attribute
> specific the xlen different to the cmd. Aka compile with rv64
On 2/14/25 11:33 PM, pan2...@intel.com wrote:
From: Pan Li
This patch would like to avoid the ICE when the target attribute
specific the xlen different to the cmd. Aka compile with rv64gc
but target attribute with rv32gcv_zbb. For example as blow:
1 │ long foo (long a, long b)
2
From: Pan Li
This patch would like to avoid the ICE when the target attribute
specific the xlen different to the cmd. Aka compile with rv64gc
but target attribute with rv32gcv_zbb. For example as blow:
1 │ long foo (long a, long b)
2 │ __attribute__((target("arch=rv32gcv_zbb")));
