Committed, thanks Juzhe.
Pan
From: juzhe.zh...@rivai.ai
Sent: Monday, October 23, 2023 3:56 PM
To: Li, Pan2 ; gcc-patches
Cc: Li, Pan2 ; Wang, Yanzhang ;
kito.cheng
Subject: Re: [PATCH v1] RISC-V: Bugfix for merging undef tmp register for trunc
LGTM
LGTM。
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2023-10-23 15:53
To: gcc-patches
CC: juzhe.zhong; pan2.li; yanzhang.wang; kito.cheng
Subject: [PATCH v1] RISC-V: Bugfix for merging undef tmp register for trunc
From: Pan Li
For trunc function autovec, there will be one step like below take MU
From: Pan Li
For trunc function autovec, there will be one step like below take MU
for the merge operand.
rtx tmp = gen_reg_rtx (vec_int_mode);
emit_vec_cvt_x_f_rtz (tmp, op_1, mask, vec_fp_mode);
The MU will leave the tmp (aka dest register) register unmasked elements
unchanged and it is undef
