RE: [PATCH v1] RISC-V: Allow RVV intrinsic for more function target

about it and update in v2. Pan -Original Message- From: Li, Pan2 Sent: Thursday, March 28, 2024 3:32 PM To: Kito Cheng Cc: gcc-patches@gcc.gnu.org; juzhe.zh...@rivai.ai; Wang, Yanzhang Subject: RE: [PATCH v1] RISC-V: Allow RVV intrinsic for more function target Thanks kito, looks missed

RE: [PATCH v1] RISC-V: Allow RVV intrinsic for more function target

Thanks kito, looks missed this part in test, let me check it out. Pan -Original Message- From: Kito Cheng Sent: Thursday, March 28, 2024 2:44 PM To: Li, Pan2 Cc: gcc-patches@gcc.gnu.org; juzhe.zh...@rivai.ai; Wang, Yanzhang Subject: Re: [PATCH v1] RISC-V: Allow RVV intrinsic for

Re: [PATCH v1] RISC-V: Allow RVV intrinsic for more function target

Just tried something interesting: $ riscv64-unknown-linux-gnu-gcc -march=rv64gc -O target_attribute_v_with_intrinsic-9.c -S # Work $ riscv64-unknown-linux-gnu-gcc -march=rv64gc_zve32x -O target_attribute_v_with_intrinsic-9.c -S # Not work Also I guess all zvk* and zvbb may also need to be added a

[PATCH v1] RISC-V: Allow RVV intrinsic for more function target

From: Pan Li In previous, we allowed the target(("arch=+v")) for a function with rv64gc build. This patch would like to support more arch options as below: * zve32x * zve32f * zve64x * zve64f * zve64d * zvfhmin * zvfh For example, we have sample code as below. vfloat32m1_t __attribute__((target