Re: [PATCH v1] RISC-V: Allow IMM operand for unsigned scalar .SAT_ADD

2024-09-03 Thread Jeff Law
On 9/2/24 5:27 AM, pan2...@intel.com wrote: From: Pan Li This patch would like to allow the IMM operand of the unsigned scalar .SAT_ADD. Like the operand 0, the operand 1 of .SAT_ADD will be zero extended to Xmode before underlying code generation. The below test suites are passed for this

[PATCH v1] RISC-V: Allow IMM operand for unsigned scalar .SAT_ADD

2024-09-02 Thread pan2 . li
From: Pan Li This patch would like to allow the IMM operand of the unsigned scalar .SAT_ADD. Like the operand 0, the operand 1 of .SAT_ADD will be zero extended to Xmode before underlying code generation. The below test suites are passed for this patch. * The rv64gcv fully regression test. gcc