Re: [PATCH V3] RISC-V: Support combine cond extend and reduce sum to widen reduce sum

Committed with splited patchs, thanks Robin. [COMMITTED] RISC-V: Split VLS avl_type from NONVLMAX avl_type https://gcc.gnu.org/pipermail/gcc-patches/2023-September/631152.html [COMMITTED V4] RISC-V: Support combine cond extend and reduce sum to widen reduce sum https://gcc.gnu.org/pipermail/gc

Re: [PATCH V3] RISC-V: Support combine cond extend and reduce sum to widen reduce sum

Hi Robin, On 2023/9/21 16:12, Robin Dapp wrote: Hi Lehua, V3 Change: Back to the original method. Was there an original method even before the first patch? Yes, this was the method that came to mind at first, and I didn't send a patch because I didn't feel like the pattern looked good :)

Re: [PATCH V3] RISC-V: Support combine cond extend and reduce sum to widen reduce sum

Hi Lehua, > V3 Change: Back to the original method. Was there an original method even before the first patch? Anyway, I prefer this v3 over the others even though the large pattern is not exactly pretty :) What about the VLS changes? Are they necessary for the patterns/tests? I mean they are re

[PATCH V3] RISC-V: Support combine cond extend and reduce sum to widen reduce sum

V3 Change: Back to the original method. This patch support combining cond extend and reduce_sum to cond widen reduce_sum like combine the following three insns: (set (reg:RVVM2HI 149) (if_then_else:RVVM2HI (unspec:RVVMF8BI [ (const_vector:RVVMF8BI repeat [