LGTM with a minor comment.
> Currently, vfwadd.wv is the pattern with (set (reg) (float_extend:(reg))
> which makes
it's minor so you can just go commit after the fix: this should be
(set (plus (reg) (float_extend:(reg)))
> combine pass faile to combine.
>
> change RTL format of vfwadd.wv -
Currently, vfwadd.wv is the pattern with (set (reg) (float_extend:(reg)) which
makes
combine pass faile to combine.
change RTL format of vfwadd.wv --> (set (float_extend:(reg) (reg)) so that
combine
PASS can combine.
gcc/ChangeLog:
* config/riscv/riscv-vector-builtins-bases.cc: Ada
