Re: [PATCH 6/7] RISC-V: Add support for the XAndesvpackfph ISA extension.

On 6/23/25 3:02 AM, KuanLin Chen wrote: Hi, This extension defines vector instructions to extract a pair of FP16 data from a floating-point register. Multiply the top FP16 data with the FP16 elements and add the result with the bottom FP16 data. gcc/ChangeLog:         * common/config/ris

[PATCH 6/7] RISC-V: Add support for the XAndesvpackfph ISA extension.

Hi, This extension defines vector instructions to extract a pair of FP16 data from a floating-point register. Multiply the top FP16 data with the FP16 elements and add the result with the bottom FP16 data. gcc/ChangeLog: * common/config/riscv/riscv-common.cc: Turn on VECTOR_ELEN_