hrist...@arm.com; juzhe.zh...@rivai.ai;
kito.ch...@gmail.com; jeffreya...@gmail.com; Robin Dapp
Subject: Re: [PATCH 4/5] RISC-V: Implement the MASK_LEN_STRIDED_LOAD{STORE}
> +(define_expand "mask_len_strided_store_"
> + [(match_operand 0 "pmode_reg_or_0_o
> +(define_expand "mask_len_strided_store_"
> + [(match_operand 0 "pmode_reg_or_0_operand")
> + (match_operand 1 "pmode_reg_or_0_operand")
> + (match_operand:V 2 "register_operand")
> + (match_operand: 3 "vector_mask_operand")
> + (match_operand 4 "autovec_length_ope
From: Pan Li
This patch would like to implment the MASK_LEN_STRIDED_LOAD{STORE} in
the RISC-V backend by leveraging the vector strided load/store insn.
For example:
void foo (int * __restrict a, int * __restrict b, int stride, int n)
{
for (int i = 0; i < n; i++)
a[i*stride] = b[i*stri
