gnu.org;
> apin...@marvell.com; Richard Earnshaw ; nd
> ; Marcus Shawcroft ; Richard
> Sandiford
> Subject: RE: [PATCH 3/7]AArch64 Add pattern for sshr to cmlt
>
>
>
> > -Original Message-
> > From: Andrew Pinski
> > Sent: Monday, October 11, 2021 8
gcc-patches@gcc.gnu.org
> > > Cc: nd ; Richard Earnshaw
> ;
> > > Marcus Shawcroft ; Kyrylo Tkachov
> > > ; Richard Sandiford
> > >
> > > Subject: [PATCH 3/7]AArch64 Add pattern for sshr to cmlt
> > >
> > > Hi All,
> > >
> >
croft ; Kyrylo Tkachov
> > ; Richard Sandiford
> >
> > Subject: [PATCH 3/7]AArch64 Add pattern for sshr to cmlt
> >
> > Hi All,
> >
> > This optimizes signed right shift by BITSIZE-1 into a cmlt operation which
> > is
> > more optimal because general
> -Original Message-
> From: Tamar Christina
> Sent: Wednesday, September 29, 2021 5:20 PM
> To: gcc-patches@gcc.gnu.org
> Cc: nd ; Richard Earnshaw ;
> Marcus Shawcroft ; Kyrylo Tkachov
> ; Richard Sandiford
>
> Subject: [PATCH 3/7]AArch64 Add pattern f
Hi All,
This optimizes signed right shift by BITSIZE-1 into a cmlt operation which is
more optimal because generally compares have a higher throughput than shifts.
On AArch64 the result of the shift would have been either -1 or 0 which is the
results of the compare.
i.e.
void e (int * restrict
