Re: [PATCH 3/7] RISC-V: Fix vector memcpy smaller LMUL generation

2024-10-18 Thread Jeff Law
On 10/18/24 7:12 AM, Craig Blackmore wrote: If riscv_vector::expand_block_move is generating a straight-line memcpy using a predicated store, it tries to use a smaller LMUL to reduce register pressure if it still allows an entire transfer. This happens in the inner loop of riscv_vector::expan

[PATCH 3/7] RISC-V: Fix vector memcpy smaller LMUL generation

2024-10-18 Thread Craig Blackmore
If riscv_vector::expand_block_move is generating a straight-line memcpy using a predicated store, it tries to use a smaller LMUL to reduce register pressure if it still allows an entire transfer. This happens in the inner loop of riscv_vector::expand_block_move, however, the vmode chosen by this l